Note that the registration desk is located at the entrance of the Conference Centre, opposite of the Turing Room. Room L120 is located at CWI (adjacent to the Conference Centre).
Friday 30 August (room L120)
|08.55-09.00||Opening/Welcome to FMICS (Turing room)|
|09.00-10.00||Jaco van de Pol (invited talk; jointly with CONCUR, Turing room)|
Concurrent Algorithms and Data Structures for Model Checking
|10.30-11.10||Davide Basile, Maurice H. ter Beek, Alessio Ferrari and Axel Legay|
Modelling and Analysing ERTMS L3 Moving Block Railway Signalling with Simulink and Uppaal SMC
|11.10-11.50||Mark Bouwman, Bob Janssen and Bas Luttik|
Formal Modelling and Verification of an Interlocking using mCRL2
|11.50-12.30||Matthias Volk, Norman Weik, Joost-Pieter Katoen and Nils Nießen|
A DFT Modeling Approach for Infrastructure Reliability Analysis of Railway Station Areas
|13.30-14.10||Industry Session: Machiel van der Bijl (Axini)|
Formal methods in industry, or what problems do companies have that FM can solve?
|14.10-14.50||Industry Session: Robert Howe (Verum)|
Why aren’t FM specialists rich(er)?
|14.50-15.00||Best Paper Award Session|
|15.30-16.10||Philipp Berger, Johanna Nellen, Joost-Pieter Katoen, Erika Abraham, Md Tawhid Bin Waez and Thomas Rambow|
Multiple Analyses, Requirements Once: simplifying testing & verification in automotive model-based development
|16.10-16.50||Martijn Goorden, Joanna van de Mortel-Fronczak, Michel Reniers, Wan Fokkink and Jacobus Rooda|
The Impact of Requirement Splitting on the Efficiency of Supervisory Control Synthesis
|16.50-17.30||Akram Idani, Yves Ledru, Abderrahim Ait Wakrime, Simon Collart- Dutilleul and Rahma Ben Ayed|
Incremental development of a safety critical system combining formal methods and DSMLs
Saturday 31 August (room L120)
|09.00-10.00||Holger Hermanns (invited talk; jointly with YR-CONCUR and TRENDS)|
Power in Low Earth Orbit. Verified.
|10.30-11.10||Benjamin Lewis, Arnd Hartmanns, Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty, Sanghamitra Roy and Zhen Zhang|
Probabilistic Verification for Reliable Network-on-Chip System Design
|11.10-11.50||Petr Ročkai and Jiri Barnat|
A Simulator for LLVM Bitcode
|11.50-12.30||Yuvaraj Selvaraj, Wolfgang Ahrendt and Martin Fabian|
Verification of Decision Making Software in an Autonomous Vehicle: An Industrial Case Study